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Title: |
Sr. PCB Designer
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Location: |
US-California
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Work History: |
EXPERIENCE:
2006 – 07 INTEL CORP. – Dupont, WA. Designed Test Boards for Intel’s next generation of high speed busses using BGA’s with large pin counts. Applied trace phasing and other techniques to maintain the Signal Integrity for differential pairs and length matching. Among these techniques were “Escape Rules”, “Length Compensation”, “Serpentine Rules” and “Via Guidelines”. I was involved in Intel’s sophisticated checking process using net meetings to broadcast job files and 350 cam files over the net using telephone conversations, instant messaging and email to evaluate these designs and bring the boards to a successful completion. Created ODB++, DXF, IDF and PDF files for manufacturing and design team analysis. Used Report Writer to generate “Length Reports”
2005 - 06 BUSTRONIC. – Fremont, CA. Extrapolated design spec’s from VME64x and VXS Bus architecture manuals to translate the data into backplanes for such companies as MIT, L3 Comm. Designed the first VXS Processor Mesh Board. My responsibilities involved calculating voltage and current requirements to selected capacitor types and quantities as well as identifying terminating resistors for bus signals. This data as well customer requested circuits were captured into Design Capture before generating a PCB. Formulated bridges that would combine the switches to the appropriate payload slots such as the Standard Star, Dual Star or the Mech configuration to meet the vita 41.7 standards. The initial design phase required setting up 400 to 600 highspeed matching diff. pairs and 6 to 10 clock lines for match lengths and tolerances. Microstrip and striplines were evaluated to meet impedance requirements. Generated all documentation to build & assemble the backplanes including creating and maintaining BOM’s and ECO’s. The last quarter of 2005 we were required to make many of the backplanes RoHS compliant. My responsibilities included training less experienced designers in Expedition. I was involved in the development of their Exp. Lib and installed M.G. software, service Pac’s, etc.
2004 - 05 MIT Lincoln Labs. – Lexington, MA. The first assignment was to reverse engineer a board that was previously designed on an obsolete software tool. Initially, Design Capture was used to create schematics. Later, I received training using Dx Designer and this became to the preferred front end tool. Out of the 22 designs, some were RF, others were digital and three of those were backplanes. Required special handling of BOM’s & PCB’s for Flight boards. Differential pairs were common; especially the backplanes. It was std practice to use Fit Check board’s to insure successful final boards. AutoCAD was preferred to generate fabrication and assembly drawings. Checkmate was used to check manufacturing issues.
2004 INTEL CORP. – Dupont, WA. Created designs for high-speed circuits to evaluate signal integrity utilizing flex & rigid flex circuits. Analyzed next generation processors & chipsets for performance and optimal route ability using 0.8mm pitch devices requiring micro & core vias. I was responsible for library parts, schematics, placement and layout which included generating all necessary documents for manufacturing. using M.G. WG2004 suite.
2003 - 04 DESIGN LINE - Contracted to do various designs using Mentor Expedition WG2000.5 Created & managed libraries (symbols, pad stacks, cells, etc). Generated schematics, & laid out of SMT PC Boards with complete docs for mixed analog & digital boards. I was assigned to design four microstrip boards to be completed in a month and half.
2001 - 02 BALL AEROSPACE - Boulder, CO
Design all of the major PC boards for “DEEP IMPACT” including the backplane using Mentor Exp. 2000A/2000.5. These boards were extremely dense & required extensive teamwork and interfacing with Elec. & Mech. Engineers. to resolve mechanical constraints and using techniques to resolve thermal radiant requirements while maintaining electronic spec’s. Designs included high-speed logic chips that required thermal analysis, with diff pairs, impedance control using FPGA packages.
1993 - 99 ROCKWELL INTERNATIONAL CORP. - Newport Beach, CA
I designed a wide variety of PC Bds. Such as Hand Held Phones with Buried, Blind, and Micro Vias, Teradyne Test boards, modems and other RF cards using Cadnetix and DDE software. I revised the entire CAD lib. Teamed up with two other senior designers & devised ways to automate process for creating parts: 1500+ footprints and over 10,000 schematic symbols. Also assigned to do a breaking system and a sensor control board for Automotive Div. Created 20-25 designs per yr, required FPGA’s & BGA,s
1992 - 92 EG&G Los Alamos, NM
Designed test equipment PCB’s using Cadx tools. Generated all BOM’s Assy & Fab dwg for Build. After completing PC Boards ahead of schedule, I was asked to train in-house designers to help them increase their output.
1990 - 91 STANFORD TELECOMM. - Santa Clara, CA
Designed GPS, RF, & Stripline Boards conforming to Mil Std 600C and other related spec’s. Generated required Dwg’s for Fab & Assy. Help Design department develop CAD procedures.
1989 - 90 MICRO COMMUNICATIONS - Santa Clara, CA
I created RF layouts with careful ground shielding and Stripline layers using Cadx and generated all related documentation for fabrication applying ANSI/IPC-SM-782 standards.
1986 - 88 HEWLETT PACKARD - Disk Memory Division - Boise, ID
Translated Calay design files to Cadx files. Developed and managed an entire Cadx library. Created schematics, designed the Disk Drive PC Bds. Dev. CAD procedures for Cadx; laid out GPS, RF, & Stripline Bds. Advised and consultanted with the Design Team to design some of their more difficult high-density PCBs for a product line of disk controllers. The challenge was to reduce the number of layers and vias that other designers had created. I instructed classes in PCB design & innovative PC design checking. Both classes were videotaped and distributed throughout HP's libraries.
1985 - 86 LARSON DAVIS LABS Pleasant Grove, UT
Designed System Analyzer Boards using Paragon Software and evaluated PCB Design CAD systems. I gave my recommendations to management and was responsible for final selection of Cadx. After purchase, developed and managed the CDX database as well as design boards for the spectrum analyzers. Incorporated PCB comp spec’s IPC-CM-770B & ANSI/IPC-S_815A.
1982 - 84 WICAT SYSTEMS, INC. - Orem, UT
Manager of Engineering Services. My responsibilities included forecasted design schedules and managed a $1.3 million dollar department budget. Managed a department of 18 designers & drafting personnel which including recommending salary actions, conducted performance appraisals, career path planning guidelines. Introduced an innovative state of the art process for designing PCB’s tripling the number of designs per year. Evaluated and advised management on the purchase and development of a CAD system for the PCB department. Involved in initiating the BOM system for materials resource planning program in engineering.
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Skills: |
* MG Exp. WG2005 Lib/Sch/PCB * Dig/Ana High Speed Design *Mil Std/IPC spec
* UNIX OS/Solaris/AutoCAD * PCB file Translations * ECL, RFI, EMI
* Teradyne Bds & PCMCIA Cards * Microstrip & Stripline * Elec/Mech Pkg
* Word/Excel/Corel/DxDsgnr * Buried/Core & Microvias * Radiant Heat
* Mentor Graphics GBOBD++ * CAM350 Version 9 * Line Phasing
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Education: |
EDUCATION: Brigham Young University - Provo, UT - 4 Yrs
VeriBest 95/Microstation PCB Training - Mt View, CA
Mentor Graphics Expedition Training - Orem, UT
DxDesigner &AutoCAD Training, MIT, MA
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