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Title: |
ASIC/FPGA/Digital/Hardware Engineer
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Location: |
US-California-Santa Barbara
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Work History: |
WORK EXPERIENCE
Test Systems Engineer: Internship at Transphorm, CA 93117 Oct 2011 to Present
•Designing and debugging test and reliability systems for semiconductor testing.
•PCB layout, design/fabrication of test fixtures using C/C++/Labview Programs.
Research Assistant at CSUN under Dr. Ramin Roosta Jan 2011 to June 2011
•Worked on Low Power Optimization of FPGA and ASICs using Design and IC compiler.
•Role was to write scripts,apply design constraints and perform power and timing analysis.
•Included RTL Synthesis, Floorplanning, Place and Route for the Physical netlist creation,
XOR clock-gating, Multi-Vt, STA, and Verilog for Design and Test Bench Verification.
Electrical Engineer: Internship at Brazen Tek, CA 91364 June 2010 to Nov 2010
•Designing, Compiling and Debugging source code written in C and VHDL/Verilog HDL.
•Modeling and Simulation using Cadence NC Verilog, Modelsim, Pspice and Matlab.
•Designing Schematics for PCB layout using Orcad Capture CIS and Orcad Layout tool.
Embedded Engineer at Sitech Electronics, Bangalore-32, India July 2008 to July 2009
•Designing and debugging in C and assembly for 8051/ARM and other embedded devices.
•Driver development for device drivers like keypad controller, LED, LCD,ADC and DAC.
•Worked with Robotics team on controlling the movement of the robot using Stepper Motors, ARM9 Microprocessor core,8051/PIC Microcontrollers and Linux Environment.
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Skills: |
TECHNICAL SKILLS
•Hardware Description Languages: Verilog HDL, VHDL.
•Programming Languages: C, Perl Scripting, C++, 8051/8086 Assembly.
•Tools: Cadence NC Verilog/Modelsim Simulators, Xilinx ISE, Synopsys Design and IC compiler, Primetime (STA), Pspice and Orcad Schematic Capture/Layout tool for PCB.
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Education: |
EDUCATION
Master of Science in Electrical Engineering May 2011
California State University, Northridge (CSUN) GPA 3.3
Bachelor of Engineering in Electronics and Communication June 2008
Atria Institute of Technology (VTU), India GPA 3.7
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NAVEEN KUMAR has endorsed 0 Members.
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