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Title: |
VLSI Engineer
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Location: |
US-California
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Work History: |
Work Experience
• University of Connecticut, Department Electrical and Computer Engineering: Assist graduate students in understanding the operation and theory of the experiments such as thermal oxidation, diffusion, photolithography (MJB3 Karl Suss Mask Aligner) and metal deposition and wet etching. (August 2010 to December 2010)
• University of Connecticut, Department Electrical and Computer Engineering: Worked as a Teaching Assistant in grading homeworks and exams (August 2010 to December 2010)
• University of Connecticut, Department Electrical and Computer Engineering: Working as a Research Assistant (January 2009 to Current)
• University of Connecticut, Department Electrical and Computer Engineering: Assisted Professor in teaching courses like Nanotechnology and Micro/opto electronic Devices etc ( January 2010 to December 2010
Back End Experience
• Two years of considerable Cleanroom Environment (Class 1000 cleanroom facility) Experience with semiconductor fabrication processes like oxidation, diffusion, photolithography, etching and metal deposition. (Jan 2008- Dec 2010)
• Design and Fabrication of QD channel FET (November 2010 to current)
• Design and Fabrication of QD Inverter: 3 state Inverter is fabricated with Si and Ge Quantum dots and simulated using Cadence (August 2008 to October 2008)
• Tandem Solar cell: Designed and implemented the simulation of an Amorphous-Si and Crystalline-Si Tandem Solar Cell (August 2008 to December 2008)
• Designed and implemented Tandem solar cell Using Matlab Program. .(December 2010 to June 2011)
Custom design Experience
• Verilog Modelsim for Logic implementation, debug and verification (since August 2010)
• Cadence tool for schematic and layout designing on Static, Dynamic and mixed signal as well as high speed designs. (August 2010 to current)
• Working on Design and implementation of ADCs and DACs using two channel FETs (35nm technology) based on BSIM and Ami05 Model in cadence tool (November 2010 to current)
• Designed and implemented Multiplier Accumulator Using Cadence tool(February 2011 to May 2011).
• 3-Bit ADCs and DACs using Two-channel FETs (45 nm tech) based on BSIM 3.2.0 and BSIM 3.2.4 and Ami 05 models (September 2010 to December 2010)
• 3-Bit ADCs and DACs using Three-channel FETs (45 nm tech) based on BSIM 3.2.0 and BSIM 3.2.4 and Ami 05 models (December 2009 to September 2010)
• 3-BitADCs and DACs using 3-state Quantum DOT Gate FETs based on BSIM 3.2.0 and BSIM 3.2.4 and Ami 05 models (September 2008 to December 2009)
Embedded System Experience
• Airport Baggage management system: Unique IDs of each passenger and their corresponding baggage are read at the checking counter and database is created which is then compared with the IDs that are read at the reconciliation Centre. If any mismatch found authorities are alerted (January 2007 to March 2007).
• Safety Guard for the Blind: Electronic safety guard system that alerts the blinds of any obstacles within one meter. The system comprises of transmitter and receiver sections. The receiver section uses an embedded system that tells the voice processor to play the recorded message in case any obstacle is detected. The embedded system is a microcontroller programmed to take the appropriate action (December 2005 to March 2006)
Experience in C
• Designed and modeled Quantum dot modulator Using C Program.(December 2010 to June 2011)
• Designed and implemented Quantum dot laser Using C Program. .(December 2010 to June 2011)
• Designed and implemented Tandem solar cell Using C Program. .(December 2010 to June 2011)
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Skills: |
Technical skills
• Programming Languages : C (Intermediate), VHDL, Verilog
• Assembly languages : 8085,8086
• Operating Systems: Microsoft Windows 9X, 2000, XP.
• Eldo SPICE (Simulation – MENTOR Tool)
• IC Station (Layout Designs - MENTOR Tool)
• Calibre (DRC, LVS & PEX)
• ModelSim6.1b (RTL coding in VHDL, Verification, Simulation)
• Leonardo Spectrum-2005b.24( Synthesis of digital systems )
• Xilinx ISE 8.1i (XST) (RTL to Implementation on FPGA’s)
• Standard Cell designing and cell Characterization using tools - Eldo SPICE, CADENCE
• Calibre, IC Station. Basic layouts using Ami 05 and TSMC technology
• RTL coding in Verilog
• Simulation, Verification and Synthesis of digital systems using ModelSim 6.1b, Leonardo Spectrum-2005b.24, Xilinx ISE 8.1i (XST)
• SILVACO (Device Modeling)
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Education: |
M.S., Electrical Engineering at University of Connecticut, CT [GPA – 3.829/4] Aug 09 - May 11
Graduate Coursework: VLSI Design and simulation with cadence, Semiconductor Devices and models and MOSFET Devices, CMOS Circuits and digital designing.
Diploma in VLSI Design, at Sandeepani School of VLSI Design, Bangalore, India [Satisfactory] Dec 07 – Aug 08
Diploma Coursework: CMOS Circuits and digital designing, High speed Dynamic CMOS Designing, CMOS Static Design and Analysis, Timing Analysis of VLSI circuits (Transistor sizing, Delay, Buffer insertion), RTL coding.
B.E., Electronics and Communication Engineering, College of Engineering Munnar, India [7/10] June 03 - Aug 07
Undergraduate Coursework: Digital Design, Digital communication, Microprocessor and Microcontroller, VLSI Design.
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Anjana has endorsed 0 Members.
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