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Title: |
Process Integration Engineer / Device Engineer
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Location: |
US-Texas-Austin
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Work History: |
Intel Corp.
August 2006 - March 2010 Hillsboro, OR
Device Engineer for the 32nm technology node
-Daily device analysis in the development of the 32nm fabrication process. Particular focus on NMOS junction engineering and gate stack development.
-Designed >90% of the MOS transistors used in 32nm process development test chip.
-Directly impacted product performance through the invention of several novel transistor enhancements.
UC Berkeley
Fall 2001 - August 2006 Berkeley, CA
Graduate Student Researcher
-Created the first-ever organic antifuse
Fabricated vertically stacked organic nonvolatile memory elements on flexible plastic substrates.
-Studied lifetime and performance enhancement in organic TFTs through thermal cycling.
-Constructed and characterized a sub-30nm top-gated organic TFT.
-Explored electron beam exposure for organic TFT device isolation.
Intel Corp.
Spring 2005 Hillsboro, OR
Device Intern for the 45nm technology node
Efficient Networks, Inc.
Summer 1999 Dallas, TX
Engineering Intern
Alcatel Network Systems
Summer 1997, 98 Richardson, TX
Engineering Intern
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Skills: |
Advanced studies in device physics and front-end fabrication technology. Developed knowledge of carrier transport in organic and inorganic semiconductors. Extended experience with cutting edge silicon technology development and microfabrication tools (Cadence, evaporators, sputtering systems, resist spinning/development tracks, optical exposure tools, e-beam lithography, plasma etching, etc.). Proficient with advanced test equipment including profilometers, SEM, HP4156 parameter analyzer, oscilliscopes, waveform generators, etc. Well acquainted with statistical analysis tools such as JMP and Statistica. Experience in Visual Basic, Java, C++, Assembly, and Scheme (dialect of LISP). Proficient in Microsoft Word, Excel, and Powerpoint.
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Education: |
UC Berkeley
2001 - 2006 Berkeley, CA
Ph.D. / Electrical Engineering - Device Physics, Fabrication
Minor in Materials Science
Thesis: Enabling Technologies for Organic Memories
GPA: 3.9
UC Berkeley
1997 - 2001 Berkeley, CA
Bachelor of Science (with honors) / Electrical Engineering and Computer Science
GPA: 3.6
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