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Title: |
Lead ASIC IC Designer
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Location: |
US-Texas-Austin
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Work History: |
Lead ASIC Design Engineer, Freescale Semiconductor Austin, Texas
o MIPI video DSI and CSI (protocol layers) Architecture, Design, and Verification.
Lead Engineer, responsible for all communication and information transfer to and from architects, chip team, and software teams.
CSI (Camera) work included; translation of MIPI input frame including timing to a standard video frame made up of HSYNC, VSYNC, and video data.
DSI (Display) work included; translation of standard video output frame including HSYNC, VSYNC, and video data to a MIPI compliant video frame including timing.
Took MIPI video algorithms from architects and defined micro-architecture per MIPI DSI and CSI2 specifications.
Coded micro-architecture in RTL using Verilog.
Synthesized RTL using Synopsys and Cadence tools to produce netlists.
Ran timing analysis on synthesized netlist using Synopsys and Cadence tools.
Ran equivalency checks to verify that the netlist and RTL were functionally equivalent using LEC.
Verified RTL using VCS and Verilog.
Ran coverage analysis on verification results using HDLscore.
Design included scan and bist support
Delivered design to chip team and actively supported chip integration, chip system test, silicon system test, and software.
Worked closely with teams in India, China, France, and Israel.
7/03-11/07
Lead ASIC Design Engineer, Motorola/Freescale Semiconductor, Austin, Texas
o NEXUS Debug Architecture, Design, and Verification.
Lead Engineer, responsible for all communication and information transfer to and from architects, chip team, and software teams.
Work included; NEXUS auxiliary bus design with memory interface, NEXUS auxiliary bus arbitrator design, and NEXUS auxiliary bus asynchronous FIFO design for clock domain crossing.
Took NEXUS debug algorithms from architects and defined micro-architecture per NEXUS IEEE-ISTO 5001 specifications.
Coded micro-architecture in RTL using Verilog.
Synthesized RTL using Synopsys and Cadence tools to produce netlists.
Ran timing analysis on synthesized netlist using Synopsys and Cadence tools.
Ran equivalency checks to verify that the netlist and RTL were functionally equivalent using LEC.
Verified RTL using VCS and Verilog.
Wrote assembly code for test vectors.
Ran coverage analysis on verification results using HDLscore.
Design included scan and bist support
Delivered design to chip team and actively supported chip integration, chip system test, silicon system test, and software.
Worked closely with teams in India, China, and Israel.
8/99-7/03
ASIC Design Engineer, Motorola Semiconductor, Austin, Texas
o BAYER Sensor Video co-processor Architecture, Design and Verification.
Took image processing algorithms from architects and defined micro-architecture.
Image processing work included; Edge enhancement, bad pixel detection, bad pixel correction, color correction, color conversion, gamma correction, and frame decimation.
Coded micro-architecture in RTL using Verilog.
Synthesized RTL using Synopsys tools to produce netlists.
Ran timing analysis on synthesized netlist using Synopsys tools.
Ran equivalency checks to verify that the netlist and RTL were functionally equivalent using LEC.
Wrote testbench and vectors in Verilog.
Verified RTL using VCS.
Ran coverage analysis on verification results using HDLscore.
Delivered design to chip team and actively supported chip integration, chip system test, silicon system test, and software.
Architecture work included; algorithm to power gate logic sections on a functional basis during the portions of the frame where each were not in use.
Control work included; I2C interface to configure and monitor sensor.
o Digital video encoder chip FPGA emulation.
Synthesized, placed and routed, and emulated video encoder using Aptix and Xilinx Virtex1000 FPGAs.
7/96-8/99
FPGA and Board Design Engineer, Motorola Cellular Infrastructure, Fort Worth, Texas
o Board Design:
Designed microprocessor and communications interface section of control, routing, and backhaul board for CDMA base stations using the Motorola MPC860 Communication Processor.
o FPGA/Board Design:
Designed ATM backhaul board for CDMA base stations using an ATM SAR and PHY chip set, and an Altera EPLD (FPGA).
o Work included: Layout support, signal integrity, software support, test/certification, factory test support, factory build support, field return support (debug).
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Skills: |
Design flow: ASIC IC; micro-architecture, rtl design, verification, synthesis, timing closure, equivalence checking, back end support, software support, and silicon validation.
Designs: Video, MIPI, Nexus, ETM, debug hardware, low power, StarCore DSP, ARM.
Tools Experience: Physical compiler, RTL compiler, Power theater, Encounter, Primetime, Mentor Schematic Capture, ORCAD, NC-Verilog, VCS, Simplify, Certify, HDL Designer Pro, Renoir, Formality, LEC, Frame Maker, UNIX, and Timing Designer
Scripting and test software: Perl, Assembly, C++.
Video Protocol Experience: MIPI DSI, MIPI CSI, MIPI DPHY, YCbCr, RGB, Bayer RGB, CCIR 656, and CCIR 601
Debug Experience: NEXUS, ETM
Communication Protocol Experience: ATM, SONET, HDLC, and T1/E1
Processors: ARM processor bus and StarCore processor bus
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Education: |
The University of Texas at Austin, Austin, Texas
• Bachelors of Science, 1996
• Major: Electrical Engineering
• Major GPA: 3.6/4.00
• GPA: 3.4/4.00
University of Oregon, Eugene, Oregon
Bachelor of Science, 1991
Major: Political Science
Minor: Economics
GPA: 3.6/4.00
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Endorsements
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Thomas has received 1 endorsement.
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Thomas has endorsed 0 Members.
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Rank |
Title |
Location |
Status |
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1.001 |
Test Engineer |
US-California-Silicon Valley/San Jose |
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