Job Description:
 |
AGENCY SEARCH ASSIGNMENT: T. Kopec and Associates
HOME Office: 800-441-0966 Pacific (access code “00”) or 541-588-6255
Physical Design Lead - Phoenix
Overview:
Company is a leading provider of multifunction connectivity and location platforms. Company’s technology portfolio includes Bluetooth, GPS, FM, Wi-Fi (IEEE802.11), UWB, NFC and other technologies to enable silicon platforms that incorporate fully integrated radio, baseband and microcontroller elements. Company’s technology has been adopted by market leaders into a wide range of mobile consumer devices such as mobile phones, automobile navigation and telematics systems, portable navigation devices (PNDs), wireless headsets, mobile computers, mobile internet devices, GPS recreational devices, digital cameras, and mobile gaming, plus a wide range of personal and commercial tracking applications. Technical Lead for the digital physical design team designing complex low-power connectivity chips using GPS, Bluetooth, FM, WiFi, NFC and other technologies for Wireless, Mobile, Consumer and other applications. The person in this key role would drive the backend design methodology and layout of the chips taped out by the US team.
Responsibilities:
Key Responsibilities:
Responsible for driving and executing the backend methodology from product inception through tapeout including block and chip-level floor planning, placement, scan-reordering, clock tree synthesis, in-place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs) and DRC/LVS/DFM checks.
Define and evolve backend low-power design methodology in 40nm technology to support aggressive low-power techniques for chips having multiple power-domains and dynamic voltage-scaling.
Automate, improve and maintain implementation methods making physical design cycle predictable and keep abreast with industry trends/tools and methodologies.
Integration of analog and RF-macros using their library models and closing timing at the interface level.
Provide technical direction, mentoring and enhance skills within the physical design team.
Interface with Design and Program Managers to define schedule, resource requirements and track backend schedule.
Qualifications:
REQUIRED SKILLS:
Strong background of deep sub-micron CMOS IC physical design including Floor planning, P&R, CTS, IR Drop Analysis, extraction. timing closure with Signal Integrity.
Proven track record of leading multiple product tapeouts with at least one using low-power methodology having multi-VDD or switchable voltage-domains.
Hands on experience and detailed knowledge of Cadence(preferred), Synopsys or Magma Physical Design-tools.
Expertise in scripting languages like PERL, TCL, AWK, shell etc.
Must be a team player with excellent verbal and written communication skills.
Around 10+ years experience with BS degree required, MS preferred.
DESIRED SKILLS:
Background in physical design of ASICs with embedded processors like ARM.
Experience with Wireless technologies like GPS/BT/WiFi.
Experience with TSMC 65/40nm Process
|
