Job Description:
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AGENCY SEARCH ASSIGNMENT: T. Kopec and Associates
HOME Office: 800-441-0966 Pacific (access code “00”) or 541-588-6255
System-On-Chip and RTL Engineer - MA
Responsible for the design and verification of a wide range of digital blocks and systems for Systems-on-Chip products. Micro-architectural specification of digital blocks. Verilog RTL design and logic synthesis. Specification and development of block- and system-level simulation environments. Verification of blocks using Verilog, SystemVerilog and C. Co-simulation of analog and digital blocks for mixed-signal verification.
Engineering degree in EE or CS, with 5+ years of semiconductor industry experience in IC design or functional verification.
Excellent Verilog design, modeling, and simulation skills are required, as well as a familiarity with industry simulation and debug tools.
Experience with SystemVerilog, VMM/OVM or C++ is a distinct advantage.
Hands-on experience with Perl, C and Matlab would also be very useful.
Mixed-signal co-simulation experience and/or digital signal processing expertise are considered a strong advantage.
A good understanding of microprocessor architectures, on-chip bus protocols such as ARM's AMBA busses and ASIC / SoC design methodologies are also considered desirable, as is experience with off-chip protocols like I2C, USB and Ethernet.
Compensation: Open
Relocation: Paid
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